Method and apparatus to analyze noise in a pulse logic digital circuit design

ABSTRACT

A method and apparatus to analyze noise in a pulse logic digital circuit comprising identifying a channel connected component (CCC) in the pulse logic digital circuit design, said CCC comprising a pulse generator. Modifying the pulse logic digital circuit by disconnecting the pulse generator form an input of the CCC in the pulse logic digital circuit design. Turning on the pulse logic digital circuit, inputting a noise signal to the CCC and monitoring an output of the pulse logic digital circuit during the time the pulse logic digital circuit is turn on.

BACKGROUND

1. Field of the Invention

The present invention is related to the field of circuit design. Inparticular, the present invention is related to method and apparatus toanalyze noise in a pulse logic digital circuit design.

2. Description of the Related Art

Static signal integrity analysis is typically used during the designverification stages of an electronic circuit to ensure the functionalityof the silicon comprising the circuit for various electrical noiseconditions. A noise problem in the design verification state of theelectronic circuit may cause functional errors or may impact thefrequency performance of the electronic circuit.

FIG. 1 illustrates an example of a conventional pulse logic digitalcircuit. Pulse logic circuits are circuits used to maximize theperformance of digital circuits and work using a pull-up/pull downnetwork. As illustrated in FIG. 1, the example pulse logic digitalcircuit 100 comprises a PMOS transistor 105 coupled to NMOS transistors110-125 as illustrated. The signal value at node N1 is maintained by akeeper circuit comprising back to back inverters 130 and 135 asillustrated. The clock signal CLK is inverted by inverter 140 to formthe NCLK signal. The CLK signal and the NCLK signal is input into thegates of transistors 110 and 120 respectively. When CLK is 0 the PMOStransistor 105 is on and precharges node N1 to a logical 1. At this timeNMOS 110 is off and therefore, the voltage value at N1 is maintainedat 1. Assuming a logical 1 at inputs A and B of NMOS transistors 115 and125 respectively, during the transition of CLK from 0 to 1, NMOStransistor 110 is turned on and NMOS transistor 120 is turns off afteran inverter delay. Thus, during the inverter delay all NMOS transistors110-125 are turned on, discharging node N1 to a logical 0, and thisresults in a logical 1 at the output of the keeper. Thus, for thecircuit of FIG. 1, only when both transistors 115 and 125 have a 1 battheir inputs the output of the pulse logic digital circuit is a 1.

Conventional verification tools are incapable of accurately analyzingpulse logic digital circuits because the conventional verification toolseither simplify the circuit to an equivalent circuit or are unable togenerate a steady state stimuli condition which tests the node N1 underevaluation conditions. For example, the conventional verification toolsmay simplify FIG. 1 to an AND gate coupled to a latch and apply steadystate signals to inputs of the equivalent circuit to analyze noiseeffects. Simplifying and/or analyzing pulse logic digital circuits usingsteady state signals is inaccurate, because during normal operation, thepulse logic digital circuits latch the signals at node N1 during theinverter delay i.e., during a transition of the CLK signal asillustrated with respect to FIG. 1. Thus, conventional verificationtools fail to indicate problems such as noise related failures in pulselogic digital circuits.

BRIEF SUMMARY OF THE DRAWINGS

Example embodiments of the present invention are illustrated in theaccompanying drawings. The accompanying drawings, however, do not limitthe scope of the present invention. Similar references in the drawingsindicate similar elements.

FIG. 1 illustrates a conventional pulse logic digital circuit.

FIG. 2 illustrates modifying the pulse logic digital circuit bydisconnecting the pulse generator from an input of the channel connectedcomponent according to one embodiment of the invention.

FIG. 3 illustrates a flow diagram for analyzing noise in a pulse logicdigital circuit according to one embodiment of the invention.

FIG. 4 illustrates a computer system for analyzing noise in a pulselogic digital circuit according to one embodiment of the invention.

DETAILED DESCRIPTION

Described is a method and apparatus to analyze noise in a pulse logicdigital circuit design comprising identifying a channel connectedcomponent (CCC) in the pulse logic digital circuit design, said CCCcomprising a pulse generator. Modifying the pulse logic digital circuitby disconnecting the pulse generator form an input of the CCC in thepulse logic digital circuit design. Turning on the pulse logic digitalcircuit, inputting a noise signal to the CCC and monitoring an output ofthe pulse logic digital circuit during the time the pulse logic digitalcircuit is turned on.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of one ofordinary skill in the art to effect such feature, structure, orcharacteristic in connection with other embodiments whether or notexplicitly described. Parts of the description are presented usingterminology commonly employed by those of ordinary skill in the art toconvey the substance of their work to others of ordinary skill in theart.

In the following description and claims, the terms “coupled” and“connected”, along with derivatives such as “communicatively coupled”may be used. It should be understood that these terms are not intendedas synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are indirect physical or electrical contact with each other. “Coupled” maymean that two or more elements are in direct physical or electricalcontact. However, “coupled” may also mean that two or more elements arenot in direct physical contact with each other, but still co-operate orinteract with each other.

FIG. 2 illustrates modifying the pulse logic digital circuit bydisconnecting the pulse generator from an input of the channel connectedcomponent according to one embodiment of the invention. FIG. 3illustrates a flow diagram for analyzing noise in a pulse logic digitalcircuit according to one embodiment of the invention. FIG. 2 illustratesthe example pulse logic digital circuit of FIG. 1 with the connection ofthe gate on NMOS transistor 220 disconnected. Noise may be defined as anunwanted signal having an AC and/or DC component that hinders theoperation of the pulse logic digital circuit. The pulse logic digitalcircuit use pulse generators to generate a pulse (pulse circuitry is notshown) that is coupled to the pulse logic digital circuit. The pulsegenerator controls the pulse characteristics (i.e., the pulse width). Inorder to analyze noise in a pulse logic digital circuit, as FIG. 3illustrates, at 305, the pulse logic digital circuit with a pulsegenerator coupled to the pulse logic digital circuit is identified. Inorder to identify a pulse logic digital circuit, in one embodiment ofthe invention, the keeper circuit is identified. Identifying the keepercircuit comprises identifying the back to back inverters 230-235. In oneembodiment of the invention, after identifying the keeper circuit, theclock driven pre-charge circuit is identified. In FIG. 2, identifyingthe pre-charge circuit comprises identifying a clock driven PMOStransistor coupled to the keeper circuit. Thus, pre-charge circuit is205 is identified.

Thereafter, channel connected components (CCCs), coupled with the pulsegenerator are identified. CCCs are well known to one having ordinaryskill in the art and basically comprise transistors wherein the channelsof the transistors are coupled to each other. In one embodiment the CCCscoupled with the pulse generator are identified by recognizing theexistence of a mutually exclusive condition for the transistors that arecoupled to the pulse generator of the CCC. In particular, adetermination is made whether given a CCC, for a steady state conditionthe transistors that control the channel of the CCC (i.e., transistors210 and 220 in FIG. 2) are not on at the same time. In FIG. 2, forsteady state inputs, when the CLK signal is a 1, the inverted clocksignal (i.e., NCLK) is a 0. Therefore, when NMOS transistor 210 is on,NMOS transistor 220 off . When the clock signal changes from a 1 to a 0,NMOS transistor 210 is off and NMOS transistor 220 is turned on. Thus, aCCC coupled with a pulse generator is identified.

Once the CCC coupled with the pulse generator is identified, in oneembodiment of the invention, at 310, the pulse generator connection atthe gate of NMOS transistor 220 is disconnected as illustrated in FIG.2. This allows a signal to be input into the gates of the transistors(transistors 210 and 220) so that the CCC transistors may be turned onsimultaneously. In one embodiment of the invention, the pulse generatorconnection at 210 may be disconnected from the gate of the transistor toallow a signal to be input into the gates of the transistors (210 and220) to turn on the transistors simultaneously. By turning on thetransistors simultaneously, e.g., by an input pulse having the pulsewidth as the pulse generated by the pulse generator that turns on thetransistor during its normal operation, a more accurate analysis of thenoise associated with pulse logic digital circuit may be performed.

In one embodiment of the invention, at 320, the NMOS transistors (210and 220) of the CCC are turned on and inputs A and B are enabled tosimulate actual voltages and signal fluctuations encountered during theoperation of the pulse logic digital circuit. In one embodiment of theinvention, to maintain the equivalent impedance at the gate of NMOStransistor 220, an impedance equivalent to the output impedance of thelocal pulse generator is coupled to the gate of the NMOS transistor 220prior to turning on the NMOS transistors.

Thus in one embodiment of the invention, the node N1 may be pre-chargedto a logic 1 prior to evaluating a noise signal. During evaluation ofthe noise signal, in one embodiment of the invention, NMOS transistor210 may be turned on by inputting a 1 at its gate. The other inputse.g., the gates of transistors 215-225 are treated as free inputs toenable worst case propagated, interconnect, and charge sharing noiseanalysis. Noise analysis as illustrated above also permits to adjust thefloat simulation time of node N1. The float simulation time is the timeduring which node N1 is tri-stated. This may occur when NMOS transistor220 is turned off.

FIG. 4 illustrates a computer system for analyzing noise in a pulselogic digital circuit according to one embodiment of the invention. Ingeneral, the computer system 400 may comprise a processing unit 402communicatively coupled through a bus 401 to system memory 413, massstorage devices 407, Input devices 406, display device 405 and networkdevices 408.

Bus 401 may be any of several types of bus structures including a memorybus, a peripheral bus, and a local bus using any of a variety of busarchitectures. System memory 413 comprises a read only memory (ROM) 404and random access memory (RAM) 403. ROM 404 comprises basic input outputsystem (BIOS) 416. BIOS 416 contain the basic routines, e.g., start uproutines, that facilitate the transfer of information between elementswithin computer system 400. RAM 403 includes cache memory and comprisesoperating system 418, application programs 420, and program data 424.Application programs 420 include the program code for implementing themethod described with respect to FIGS. 2-3 above. Program data 424 mayinclude data generated by application programs 420. Mass storage device407 represents a persistent data storage device, such as a floppy diskdrive, fixed disk drive (e.g., magnetic, optical, magneto-optical, orthe like), or streaming tape drive. Mass storage device 407 may storeapplication programs 428, operating system 426 for computer system 400,and program data 430. Application programs 428 and program data 430stored on mass storage devices 407 may include the application programs420 and program data 424 stored in RAM 403. One embodiment of theinvention may be stored entirely as a software product on mass storagedevice 407. Embodiments of the invention may be represented as asoftware product stored on a machine-readable medium (also referred toas a computer-accessible medium, a machine-accessible medium, or aprocessor-accessible medium). The machine-readable medium may be anytype of magnetic, optical, or electrical storage medium including adiskette, CD-ROM, memory device (volatile or non-volatile), or similarstorage mechanism. The machine-readable medium may contain various setsof instructions, code sequences, configuration information, or otherdata. Those of ordinary skill in the art will appreciate that otherinstructions and operations necessary to implement the describedinvention may also be stored on the machine-readable medium. Oneembodiment of the invention may be embedded in a hardware product, forexample, in a printed circuit board, in a special purpose processor, orin a specifically programmed logic device communicatively coupled to bus401. Processing unit 402 may be any of a wide variety of general-purposeprocessors or microprocessors (such as the Pentium® processor familymanufactured by Intel® Corporation), a special purpose processor, or aspecifically programmed logic device. Processing unit 402 is operable toreceive instructions which, when executed by the processing unit causethe processing unit to execute application programs 420.

Display device 405 is coupled to processing unit 402 through bus 401 andprovides graphical output for computer system 400. Input devices 406such as a keyboard or mouse are coupled to bus 401 for communicatinginformation and command selections to processing unit 402. Other inputdevices may include a microphone, joystick, game pad, scanner, or thelike. Also coupled to processing unit 402 through bus 401 is aninput/output interface (not shown) which can be used to control andtransfer data to electronic devices (printers, other computers, etc.)connected to computer system 400. Computer system 400 includes networkdevices 408 for connecting computer system 400 to one or more remotedevices (e.g., the receiving node) 412 via network 414. Remote device412 may be another personal computer, a server, a router, a network PC,a wireless device or other common network node and typically includesone or more of the elements described above with respect to computersystem 400. Network devices 408, may include a network interface forcomputer system 400, Ethernet devices, network adapters, phone jacks,modems, and satellite links. It will be apparent to one of ordinaryskill in the art that other network devices may also be utilized.

Thus, a method and apparatus for analyzing noise in a pulse logicdigital circuit has been disclosed. While there has been illustrated anddescribed what are presently considered to be example embodiments of thepresent invention, it will be understood by those skilled in the artthat various other modifications may be made, and equivalents may besubstituted, without departing from the true scope of the invention.Additionally, many modifications may be made to adapt a particularsituation to the teachings of the present invention without departingfrom the central inventive concept described herein. Therefore, it isintended that the present invention not be limited to the particularembodiments disclosed, but that the invention include all embodimentsfalling within the scope of the appended claims.

1. An method for analyzing noise in a pulse logic digital circuit designcomprising: identifying a channel connected component (CCC) in the pulselogic digital circuit design, said CCC comprising a pulse generator;modifying the pulse logic digital circuit by disconnecting the pulsegenerator from an input of the CCC in the pulse logic digital circuitdesign; turning on the pulse logic digital circuit; and inputting anoise signal to the CCC and monitoring an output of the pulse logicdigital circuit during the time the pulse logic digital circuit isturned on.
 2. The method of claim 1 wherein identifying a CCC in thepulse logic digital circuit design, said CCC comprising a local pulsegenerator comprises the local pulse generator coupled to at least onegate of one or more transistors comprising the CCC.
 3. The method ofclaim 2 wherein identifying a CCC comprises identifying the one or moretransistors comprising the CCC, such that for steady state voltagesinput to the CCC, if a first transistor comprising the CCC is on then asecond transistor comprising the CCC is off prior to the modification ofthe pulse logic digital circuit design.
 4. The method of claim 1 whereinmodifying the pulse logic digital circuit by disconnecting the localpulse generator form an input of the CCC in the pulse logic digitalcircuit design comprises adding an impedance equivalent to the outputimpedance of the local pulse generator to an input of the CCC.
 5. Themethod of claim 1 wherein turning on the pulse logic digital circuitcomprises turning on at least two transistors comprising the CCC foralternating current and direct current noise analysis.
 6. An apparatusto analyze noise in a pulse logic digital circuit comprising: a memory;a processor; and a bus coupled to the memory and the processor, theprocessor to identify a channel connected component (CCC) in the pulselogic digital circuit design, said CCC comprising a pulse generator;modify the pulse logic digital circuit by disconnecting the pulsegenerator from an input of the CCC in the pulse logic digital circuitdesign; turn on the pulse logic digital circuit; input a noise signal tothe CCC; and monitor an output of the pulse logic digital circuit duringthe time the pulse logic digital circuit is turned on.
 7. The apparatusof claim 6 wherein the processor to identify a CCC in the pulse logicdigital circuit design, said CCC comprising a local pulse generatorcomprises the processor to identify a local pulse generator coupled toat least one gate of one or more transistors comprising the CCC.
 8. Theapparatus of claim 7 wherein the processor to identify a CCC comprisesthe processor to identify the one or more transistors comprising theCCC, such that for steady state voltages input to the CCC, if a firsttransistor comprising the CCC is on then a second transistor comprisingthe CCC is off prior to the modification of the pulse logic digitalcircuit design.
 9. The apparatus of claim 6 wherein the processor tomodify the pulse logic digital circuit by disconnecting the local pulsegenerator form an input of the CCC in the pulse logic digital circuitdesign comprises the processor to add an impedance equivalent to theoutput impedance of the local pulse generator to an input of the CCC.10. The apparatus of claim 6 wherein the processor to turn on the pulselogic digital circuit comprises the processor to turn on at least onetransistor comprising the CCC for alternating current and direct currentnoise analysis.
 11. An article of manufacture for inserting a flip-flopin a circuit design between a driver and a receiver comprising: amachine-accessible medium including instructions that, when executed bya machine, causes the machine to perform operations comprisingidentifying a channel connected component (CCC) in the pulse logicdigital circuit design, said CCC comprising a pulse generator; modifyingthe pulse logic digital circuit by disconnecting the pulse generatorfrom an input of the CCC in the pulse logic digital circuit design;turning on the pulse logic digital circuit; and inputting a noise signalto the CCC and monitoring an output of the pulse logic digital circuitduring the time the pulse logic digital circuit is turned on.
 12. Thearticle of manufacture of claim 11 wherein said instructions foridentifying a CCC in the pulse logic digital circuit design, said CCCcomprising a local pulse generator comprises further instructions foridentifying the local pulse generator coupled to at least one gate ofone or more transistors comprising the CCC.
 13. The article ofmanufacture of claim 12 wherein said instructions for identifying a CCCcomprises further instructions for identifying the one or moretransistors comprising the CCC, such that for steady state voltagesinput to the CCC, if a first transistor comprising the CCC is on then asecond transistor comprising the CCC is off prior to the modification ofthe pulse logic digital circuit design.
 14. The article of manufactureof claim 11 wherein said instructions for modifying the pulse logicdigital circuit by disconnecting the local pulse generator form an inputof the CCC in the pulse logic digital circuit design comprises furtherinstructions for adding an impedance equivalent to the output impedanceof the local pulse generator to an input of the CCC.
 15. The article ofmanufacture of claim 11 wherein said instructions for turning on thepulse logic digital circuit comprises further instructions for turningon at least two transistors comprising the CCC for alternating currentand direct current noise analysis.